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AD813 rev. b a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. single supply, low power triple video amplifier pin configuration 14-lead dip and soic disable1 disable2 out2 Cin2 +in1 Cin1 out1 disable3 v s + +in2 v s C 1 2 14 13 5 6 7 10 9 8 3 4 12 11 AD813 +in3 Cin3 out3 features low cost three video amplifiers in one package optimized for driving cables in video systems excellent video specifications (r l = 150 v ) gain flatness 0.1 db to 50 mhz 0.03% differential gain error 0.06 8 differential phase error low power operates on single +3 v to 6 15 v power supplies 5.5 ma/amplifier max power supply current high speed 125 mhz unity gain bandwidth (C3 db) 500 v/ m s slew rate high speed disable function per channel turn-off time 80 ns easy to use 50 ma output current output swing to 1 v of rails applications video line driver lcd drivers computer video plug-in boards ultrasound rgb amplifier ccd based systems 50 mhz while offering differential gain and phase error of 0.03% and 0.06 . this makes the AD813 ideal for broadcast and consumer video electronics. the AD813 offers low power of 5.5 ma per amplifier max and runs on a single +3 v power supply. the outputs of each ampli- fier swing to within one volt of either supply rail to easily accom- modate video signals. while operating on a single +5 v supply the AD813 still achieves 0.1 db flatness to 20 mhz and 0.05% & 0.05 of differential gain and phase performance. all this is offered in a small 14-lead plastic dip or soic package. these features make this triple amplifier ideal for portable and battery powered applications where size and power are critical. the outstanding bandwidth of 125 mhz along with 500 v/ m s of slew rate make the AD813 useful in many general purpose, high speed applications where a single +3 v or dual power supplies up to 15 v are needed. furthermore the AD813 contains a high speed disable function for each amplifier in order to power down the amplifier or high impedance the output. this can then be used in video multiplexing applications. the AD813 is avail- able in the industrial temperature range of C40 c to +85 c in plastic dip and soic packages as well as chips. product description the AD813 is a low power, single supply triple video amplifier. each of the three current feedback amplifiers has 50 ma of output current, and is optimized for driving one back-terminated video load (150 w ). the AD813 features gain flatness of 0.1 db to 10 90 100 0% 5v 500mv 500ns figure 2. channel switching characteristics for a 3:1 mux 100k 1m 100m 10m frequency C hz 0 0.2 0.1 C0.1 C0.2 C0.3 C0.4 normalized gain C db C0.5 3v 6 15v 5v g = +2 r l = 150 v 6 5v figure 1. fine scale gain flatness vs. frequency, g = +2, r l = 150 w one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
model AD813a conditions v s min typ max units dynamic performance C3 db bandwidth g = +2, no peaking 5 v 45 65 mhz 15 v 75 100 mhz bandwidth for 0.1 db flatness g = +2 5 v 15 25 mhz 15 v 25 50 mhz slew rate 1 g = +2, r l = 1 k w 5 v 150 v/ m s 15 v 150 250 v/ m s g = C1, r l = 1 k w 5 v 225 v/ m s 15 v 450 v/ m s settling time to 0.1% g = C1, r l = 1 k w v o = 3 v step 5 v 50 ns v o = 10 v step 15 v 40 ns noise/harmonic performance total harmonic distortion f c = 1 mhz, r l = 1 k w 15 v C90 dbc input voltage noise f = 10 khz 5 v, 15 v 3.5 nv ? hz input current noise f = 10 khz, +in 5 v, 15 v 1.5 pa ? hz Cin 5 v, 15 v 18 pa ? hz differential gain error ntsc, g = 2, r l = 150 w 5 v 0.08 % 15 v 0.03 0.09 % differential phase error 5 v 0.13 degrees 15 v 0.06 0.12 degrees dc performance input offset voltage 5 v, 15 v 2 5 mv t min Ct max 12 mv offset drift 5 v, 15 v 15 m v/ c Cinput bias current 5 v, 15 v 5 30 m a t min Ct max 35 m a +input bias current 5 v, 15 v 0.5 1.7 m a t min Ct max 2.5 m a open-loop voltage gain v o = 2.5 v, r l = 150 w 5 v 69 76 db t min Ct max 66 db v o = 10 v, r l = 1 k w 15 v 73 82 db t min Ct max 72 db open-loop transresistance v o = 2.5 v, r l = 150 w 5 v 300 500 k w t min Ct max 200 k w v o = 10 v, r l = 1 k w 15 v 400 900 k w t min Ct max 300 k w input characteristics input resistance +input 15 v 15 m w Cinput 15 v 65 w input capacitance +input 15 v 1.7 pf input common mode 5 v 4.0 v voltage range 15 v 13.5 v common-mode rejection ratio input offset voltage v cm = 2.5 v 5 v 54 58 db Cinput current 23 m a/v input current 0.07 0.15 m a/v input offset voltage v cm = 10 v 15 v 57 62 db Cinput current 1.5 3.0 m a/v +input current 0.05 0.1 m a/v dual supply (@ t a = +25 8 c, r l = 150 v , unless otherwise noted) AD813Cspecifications rev. b C2C
model AD813a conditions v s min typ max units output characteristics output voltage swing r l = 150 w , t min Ct max 5 v 3.5 3.8 v r l = 1 k w , t min Ct max 15 v 13.6 14.0 v output current 5 v 25 40 ma 15 v 30 50 ma short circuit current g = +2, r f = 715 w 15 v 100 ma v in = 2 v matching characteristics dynamic crosstalk g = +2, f = 5 mhz 5 v, 15 v C65 db gain flatness match g = +2, f = 40 mhz 15 v 0.1 db dc input offset voltage t min Ct max 5 v, 15 v 0.5 3.5 mv Cinput bias current t min Ct max 5 v, 15 v 2 25 m a power supply operating range 1.2 18 v quiescent current per amplifier 5 v 3.5 4.0 ma 15 v 4.5 5.5 ma t min Ct max 15 v 6.7 ma quiescent current, powered down per amplifier 5 v 0.5 0.65 ma 15 v 0.75 1.0 ma power supply rejection ratio input offset voltage v s = 1.5 v to 15 v 72 80 db Cinput current 0.3 0.8 m a/v +input current 0.005 0.05 m a/v disable characteristics off isolation f = 5 mhz 5 v, 15 v C57 db off output impedance g = +1 5 v, 15 v 12.5 pf channel-to-channel 2 or 3 channels 5 v, 15 v C65 db isolation mux, f = 5 mhz turn-on time 5 v, 15 v 100 ns turn-off time 80 ns notes 1 slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain. specifications subject to change without notice. AD813 rev. b C3C
model AD813a conditions v s min typ max units dynamic performance C3 db bandwidth g = +2, no peaking +5 v 35 50 mhz +3 v 25 40 mhz bandwidth for 0.1 db flatness g = +2 +5 v 12 20 mhz +3 v 8 15 mhz slew rate 1 g = +2, r l = 1 k w +5 v 100 v/ m s +3 v 50 v/ m s noise/harmonic performance input voltage noise f = 10 khz +5 v, +3 v 3.5 nv ? hz input current noise f = 10 khz, +in +5 v, +3 v 1.5 pa ? hz Cin +5 v, +3 v 18 pa ? hz differential gain error 2 ntsc, g = +2, r l = 150 w +5 v 0.05 % g = +1 +3 v 0.2 % differential phase error 2 g = +2 +5 v 0.05 degrees g = +1 +3 v 0.2 degrees dc performance input offset voltage +5 v, +3 v 1.5 5 mv t min Ct max 10 mv offset drift +5 v, +3 v 7 m v/ c Cinput bias current +5 v, +3 v 7 30 m a t min Ct max 40 m a +input bias current +5 v, +3 v 0.5 1.7 m a t min Ct max 2.5 m a open-loop voltage gain v o = +2.5 v p-p +5 v 65 70 db v o = +0.7 v p-p +3 v 69 db open-loop transresistance v o = +3 v p-p +5 v 180 300 k w v o = +1 v p-p +3 v 225 k w input characteristics input resistance +input +5 v, +3 v 15 m w Cinput +5 v 90 w input capacitance +input 2 pf input common mode +5 v 1.0 4.0 v voltage range +3 v 1.0 2.0 v common-mode rejection ratio input offset voltage v cm = 1.25 v to 3.75 v +5 v 54 58 db Cinput current 3 6.5 m a/v +input current 0.1 0.2 m a/v input offset voltage v cm = 1 v to 2 v +3 v 56 db Cinput current 3.5 m a/v +input current 0.1 m a/v output characteristics output voltage swing p-p r l = 150 w , t min Ct max +5 v 3.0 3.2 v p-p +3 v 1.0 1.3 v p-p output current +5 v 20 30 ma +3 v 15 25 ma short circuit current g = +2, r f = 715 w +5 v 40 ma v in = 1 v AD813Cspecifications single supply (@ t a = +25 8 c, r l = 150 v , unless otherwise noted) C4C rev. b
ordering guide temperature package package model range description options AD813an C40 c to +85 c 14-lead plastic dip n-14 AD813ar-14 C40 c to +85 c 14-lead plastic soic r-14 AD813achips C40 c to +85 c die form AD813ar-reel 13" reel AD813ar-reel7 7" reel 5962-9559601m2a* C55 c to +125 c 20-lead lcc *refer to official dscc drawing for tested specifications and pin configuration. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 watts small outline (r) . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 watts input voltage (common mode) . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range n, r . . . . . . . . C65 c to +125 c operating temperature range AD813a . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 14-lead plastic dip package: q ja = 75 c/w 14-lead soic package: q ja = 120 c/w AD813 model AD813a conditions v s min typ max units matching characteristics dynamic crosstalk g = +2, f = 5 mhz +5 v, +3 v C65 db gain flatness match g = +2, f = 20 mhz +5 v, +3 v 0.1 db dc input offset voltage t min Ct max +5 v, +3 v 0.5 3.5 mv Cinput bias current t min Ct max +5 v, +3 v 2 25 m a power supply operating range 2.4 36 v quiescent current per amplifier +5 v 3.2 4.0 ma +3 v 3.0 4.0 ma t min Ct max +5 v 5.0 ma quiescent current, powered down per amplifier +5 v 0.4 0.6 ma +3 v 0.4 0.5 ma power supply rejection ratio input offset voltage v s = +3.0 v to +30 v 76 db Cinput current 0.3 m a/v +input current 0.005 m a/v disable characteristics off isolation f = 5 mhz +5 v, +3 v C55 db off output impedance g = +1 +5 v, +3 v 13 pf channel-to-channel 2 or 3 channel +5 v, +3 v C65 db isolation mux, f = 5 mhz turn-on time +5 v, +3 v 100 ns turn-off time 80 ns transistor count 111 notes 1 slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain. 2 single supply differential gain and phase are measured with the ac coupled circuit of figure 52. specifications subject to change without notice. C5C rev. b
AD813 rev. b C6C metalization photo dimensions shown in inches and (mm). 2.5 0.5 C50 80 2.0 1.0 C40 1.5 010 C10 C20 C30 20 30 40 50 60 70 90 ambient temperature C c maximum power dissipation C watts 14-lead soic t j = +150 c 14-lead dip package figure 3. maximum power dissipation vs. ambient temperature maximum power dissipation the maximum power that can be safely dissipated by the AD813 is limited by the associated rise in junction temperature. the maximum safe junction temperature for the plastic encap- sulated parts is determined by the glass transition temperature of the plastic, about 150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the AD813 is internally short circuit protected, this may not be enough to guarantee that the maximum junction tem- perature (150 c) is not exceeded under all conditions. to ensure proper operation, it is important to observe the derating curves. it must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. this power must be included when computing the junction temperature rise due to total internal power. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD813 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device 12 +in2 10 +in3 v s C 11 v s C 11 v s C 11 9 Cin3 8 out3 6 Cin1 5 +in1 4 v s + disable1 1 out2 14 Cin2 13 7 out1 disable2 2 3 disable3 0.057 (1.45) 0.124 (3.15)
AD813 rev. b C7C figure 5. output voltage swing vs. supply voltage figure 8 supply current vs. supply voltage at low voltages figure 9. input bias current vs. junction temperature figure 6. output voltage swing vs. load resistance 13 8 11 9 10 12 16 2 0 14 12 10 8 6 4 supply voltage C volts supply current C ma t a = +25 c figure 4. input common-mode voltage range vs. supply voltage figure 7. supply current vs. junction temperature 20 0 020 15 5 5 10 10 15 supply voltage C 6 volts output voltage C v p-p r l = 150 v no load 20 0 020 15 5 5 10 10 15 supply voltage C 6 volts common-mode voltage range C 6 volts 25 C25 C10 C20 C15 5 C5 0 10 15 20 C60 140 C40 120 100 80 60 40 20 0 C20 input bias current C m a junction temperature C c +i b , v s = 6 5v, 6 15v Ci b , v s = 6 15v Ci b , v s = 6 5v 20 8 14 10 12 18 16 140 C40 C60 120 80 60 40 100 20 0 C20 junction temperature C c supply current C ma v s = 6 15v v s = 6 5v 30 15 0 10 100 10k 1k 10 5 20 25 load resistance C v output voltage C v p-p 6 15v supply 6 5v supply
AD813 rev. b C8C figure 10. input offset voltage vs. junction temperature figure 13. linear output current vs. supply voltage figure 12. linear output current vs. junction temperature figure 15. output resistance vs. frequency, disabled state 100k 100m 10m 1m 10k 0.01 1k 10 1 0.1 100 frequency C hz closed-loop output resistance C v 5v s 15v s g = +2 figure 14. closed-loop output resistance vs. frequency figure 11. short circuit current vs. junction temperature 160 40 100 60 80 140 120 140 C40 C60 120 80 60 40 100 20 0 C20 junction temperature C c short circuit current C ma v s = 6 15v sink source 1m 100m 10m 100k 100 1m 10k 1k 100k frequency C hz w output resistance C v 70 20 50 30 40 60 20 5 015 10 supply voltage C 6 volts output current C ma 80 20 50 30 40 70 60 140 C40 C60 120 80 60 40 100 20 0 C20 junction temperature C c output current C ma v s = 6 15v v s = 6 5v 4 C16 C10 C14 C12 C4 C8 C6 C2 0 2 140 C40 C60 120 100 80 60 40 20 0 C20 input offset voltage C mv junction temperature C c v s = 6 15v v s = 6 5v
AD813 rev. b C9C figure 19. open-loop transimpedance vs. frequency (relative to 1 w ) figure 16. input current and voltage noise vs. frequency figure 20. harmonic distortion vs. frequency figure 17. common-mode rejection vs. frequency figure 21. output swing and error vs. settling time figure 18. power supply rejection vs. frequency settling time C ns output swing from 6 v to 0 10 C10 C4 C8 20 C6 2 C2 0 4 6 8 80 40 60 gain = C1 v s = 6 15v 1% 0.1% 0.025% frequency C hz power supply rejection C db 80 40 0 10k 100k 100m 10m 1m 20 60 50 30 10 70 6 15v 6 1.5v 100 10 1 10 100 100k 10k 1k frequency C hz voltage noise C nv/ hz 100 10 1 current noise C pa/ hz inverting input current noise voltage noise noninverting input current noise 10k 100k 100m 10m 1m frequency C hz 90 60 50 70 80 20 10 30 40 common-mode rejection C db 681 v v out v in 681 v v s = 6 15v v s = 3v 681 v 681 v 10k 100k 100m 10m 1m frequency C hz 100 40 120 60 80 transimpedance C db 0 C45 C90 C135 C180 phase C degrees phase gain v s = 3v v s = 6 15v v s = 3v v s = 6 15v C30 frequency C hz harmonic distortion C dbc 1k C130 10k 100k 1m 10m 100m C70 C50 C110 C90 v s = 6 15v 2nd harmonic v s = 6 5v 2nd 3rd g = +2 v o = 2v p-p v s = 6 15v: r l = 1k v v s = 6 5v: r l = 150 v 3rd harmonic v s = 6 5v
AD813 rev. b C10C figure 22. slew rate vs. output step size figure 24. closed-loop gain and phase vs. frequency, g = +1 figure 26. small signal pulse response, gain = +1, (r f = 750 w , r l = 150 w , v s = 5 v) figure 23. large signal pulse response, gain = +1, (r f = 750 w , r l = 150 w , v s = 5 v) figure 25. maximum slew rate vs. supply voltage figure 27. C3 db bandwidth vs. supply voltage, g = +1 2v 2v 50ns aaa aaa aaa aaa a a a a a a a a a a a a a a a aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aaa a a a a a a a aa aa a a a a a a a aa a a a a a a aa a a a a aa aa a a aa a a a aa aa aa aa a aa a aa aa a a aa v in v out a a a a a a a a a a a a a a a a a a a a a a a a a a aaa aaa 10 90 100 0% 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain C db +90 0 C90 C180 C270 phase shift C degrees 5v 3v phase gain v s = 6 15v 6 5v 3v 5v v s = 6 15v 6 5v 90 100 10 0% 500mv 20ns 500mv v in v out 40 80 60 100 120 140 216 14 12 10 8 6 4 supply voltage C 6 volts C3db bandwidth C mhz r f = 750 v r f = 1k v r f = 866 v r l = 150 v supply voltage C 6 volts slew rate C v/ m s 700 0 300 100 200 600 400 500 15.0 1.5 0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 g = C1 g = +10 g = +2 g = +1 output step size C v p - p slew rate C v/ m s 1000 0 300 100 200 600 400 500 700 800 900 10 1 09 67 45 8 3 2 v s = 6 15v r l = 500 v g = C1 g = +10 g = +2 g = +1
AD813 rev. b C11C figure 28. large signal pulse response, gain = +10, (r f = 357 w , r l = 500 w , v s = 15 v) figure 29. closed-loop gain and phase vs. frequency, g = +10, r l = 150 w figure 30. C3 db bandwidth vs. supply voltage, g = +10, r l = 150 w figure 31. small signal pulse response, gain = +10, (r f = 357 w , r l = 150 w , v s = 5 v) 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain (normalized) C db 0 C90 C180 C270 phase shift C degrees 3v 5v 5v g = +10 r l = 150 v phase gain 6 5v v s = 6 15v 3v 6 5v v s = 6 15v figure 33. C3 db bandwidth vs. supply voltage, g = +10, r l = 1 k w figure 32. closed-loop gain and phase vs. frequency, g = +10, r l = 1 k w 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain (normalized) C db 3v 5v 6 5v 5v 0 C90 C180 C270 phase shift C de g rees C360 3v phase gain 6 5v g = +10 r l = 1k v v s = 6 15v v s = 6 15v 216 14 12 10 8 6 4 supply voltage C 6 volts C3db bandwidth C mhz 40 30 70 50 60 80 90 20 r f = 357 v r f = 649 v r f = 154 v g = +10 r l = 1k v 216 14 12 10 8 6 4 supply voltage C 6 volts C3db bandwidth C mhz 30 20 60 40 50 70 80 r f = 154 v peaking 1db g = +10 r l = 150 v r f = 357 v r f = 649 v 10 90 100 0% 50mv 20ns 500mv v in v out 10 90 100 0% 500mv 50ns 500mv v in v out
AD813 rev. b C12C 90 0% 2v 10 100 50ns 2v figure 34. large signal pulse response, gain = C1, (r f = 750 w , r l = 150 w , v s = 5 v) 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain C db 5v 6 5v 5v 0 C90 C180 C270 phase shift C de g rees 3v phase gain 6 5v g = C1 r l = 150 v v s = 6 15v v s = 6 15v 3v figure 35. closed-loop gain and phase vs. frequency, g = C1, r l = 150 w 216 14 12 10 8 6 4 supply voltage C 6 volts C3db bandwidth C mhz 60 50 90 70 80 100 110 peaking 1.0db r f = 681 v 40 peaking 0.2db r f = 715 v g = C1 r l = 150 v figure 36. C3 db bandwidth vs. supply voltage, g = C1, r l = 150 w 10 90 100 0% 500mv 500mv 20ns figure 37. small signal pulse response, gain = C1, (r f = 750 w , r l = 150 w , v s = 5 v) 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain (normalized) C db 5v 6 5v 0 C90 C180 C270 phase shift C de g rees 3v phase gain 6 5v g = C10 r l = 1k v v s = 6 15v v s = 6 15v 3v 5v figure 38. closed-loop gain and phase vs. frequency, g = C10, r l = 1 k w 216 14 12 10 8 6 4 supply voltage C 6 volts C3db bandwidth C mhz 40 30 70 50 60 80 20 r f = 154 v g = C10 r l = 1k v r f = 357 v r f = 649 v figure 39. C3 db bandwidth vs. supply voltage, g = C10, r l = 1 k w
AD813 rev. b C13C general consideration the AD813 is a wide bandwidth, triple video amplifier that offers a high level of performance on less than 5.5 ma per am- plifier of quiescent supply current. with its fast acting power down switch, it is designed to offer outstanding functionality and performance at closed-loop inverting or noninverting gains of one or greater. built on a low cost, complementary bipolar process, and achiev- ing bandwidth in excess of 100 mhz, differential gain and phase errors of better than 0.1% and 0.1 (into 150 w ), and output current greater than 40 ma, the AD813 is an exceptionally efficient video amplifier. using a conventional current feedback architecture, its high performance is achieved through careful attention to design details. choice of feedback & gain resistors because it is a current feedback amplifier, the closed-loop band- width of the AD813 depends on the value of the feedback resis- tor. the bandwidth also depends on the supply voltage. in addition, attenuation of the open-loop response when driving load resistors less than about 250 w will also affect the band- width. table i contains data showing typical bandwidths at different supply voltages for some useful closed-loop gains when driving a load of 150 w . (bandwidths will be about 20% greater for load resistances above a few hundred ohms.) table i. C3 db bandwidth vs. closed-loop gain and feedback resistor , (r l = 150 v ) v s (v) gain r f ( v ) bw (mhz) 15 +1 866 125 +2 681 100 +10 357 60 C1 681 100 C10 357 55 5 +1 750 75 +2 649 65 +10 154 40 C1 649 70 C10 154 40 +5 +1 715 60 +2 619 50 +10 154 30 C1 619 50 C10 154 30 +3 +1 681 50 +2 619 40 +10 154 25 C1 619 40 C10 154 20 the choice of feedback resistor is not critical unless it is impor- tant to maintain the widest, flattest frequency response. the resistors recommended in the table are those (metal film values) that will result in the widest 0.1 db bandwidth. in those appli- cations where the best control of the bandwidth is desired, 1% metal film resistors are adequate. wider bandwidths can be attained by reducing the magnitude of the feedback resistor (at the expense of increased peaking), while peaking can be reduced by increasing the magnitude of the feedback resistor. to estimate the C3 db bandwidth for closed-loop gains or feed- back resistors not listed in the above table, the following two pole model for the AD813 may be used: a g s rgrc f s r gr c cl fint fint = + ++ + ? ? 2 2 2 1 () () p where: a cl = closed-loop gain from transcapacitance g = 1 + r f /r g r in = input resistance of the inverting input c t = transcapacitance, which forms the open-loop dominant pole with the transresistance r f = feedback resistor r g = gain resistor f 2 = frequency of second (nondominant) pole s =2 p j f appropriate values for the model parameters at different supply voltages are listed in table ii. reasonable approximations for these values at supply voltages not found in the table can be obtained by a simple linear interpolation between those tabu- lated values which bracket the desired condition. table ii. two pole model parameters at various supplies v s (v) r in ( v )c t (pf) f 2 (mhz) 15 85 2.5 150 5 90 3.8 125 +5 105 4.8 105 +3 115 5.5 95 as discussed in many amplifier and electronics textbooks (such as roberges operational amplifiers: theory and practice ), the C3 db bandwidth for the 2-pole model can be obtained as: f 3 = f n 1 - 2 d 2 + (2 - 4 d 2 + 4 d 4 ) 1/2 [] 1/2 where: f n = f 2 ( r f + gr in ) c t ? ? 1/2 and: d = 1 2 f 2 ( r f + gr in ) c t [] 1/2 this model will predict C3 db bandwidth within about 10% to 15% of the correct value when the load is 150 w . however, it is not accurate enough to predict either the phase behavior or the frequency response peaking of the AD813.
AD813 rev. b C14C printed circuit board layout guidelines as with all wideband amplifiers, printed circuit board parasitics can affect the overall closed-loop performance. most important for controlling the 0.1 db bandwidth are stray capacitances at the output and inverting input nodes. increasing the space be- tween signal l ines and ground plane will minimize the coupling. also, signal lines connecting the feedback and gain resistors should be kept short enough that their associated inductance does not cause high frequency gain errors. power supply bypassing adequate power supply bypassing can be very important when optimizing the performance of high speed circuits. inductance in the supply leads can (for example) contribute to resonant circuits that produce peaking in the amplifiers response. in addition, if large current transients must be delivered to a load, then large (greater than 1 m f) bypass capacitors are required to produce the best settling time and lowest distortion. although 0.1 m f capacitors may be adequate in some applications, more elaborate bypassing is required in other cases. when multiple bypass capacitors are connected in parallel, it is important to be sure that the capacitors themselves do not form resonant circuits. a small (say 5 w ) resistor may be required in series with one of the capacitors to minimize this possibility. as discussed below, power supply bypassing can have a signifi- cant impact on crosstalk performance. achieving low crosstalk measured crosstalk from the output of amplifier 2 to the input of amplifier 1 of the AD813 is shown in figure 40. all other crosstalk combinations, (from the output of one amplifier to the input of another), are a few db better than this due to the addi- tional distance between critical signal nodes. 100k 1m 100m 10m frequency C hz C50 C30 C40 C60 C70 C80 C90 crosstalk C db r l = 150 v C20 C10 C100 C110 figure 40. worst case crosstalk vs. frequency a carefully laid-out pc board should be able to achieve the level of crosstalk shown in the figure. the most significant contribu- tors to difficulty in achieving low crosstalk are inadequate power supply bypassing, overlapped input and/or output signal paths, and capacitive coupling between critical nodes. the bypass capacitors must be connected to the ground plane at a point close to and between the ground reference points for the loads. (the bypass of the negative power supply is particularly important in this regard.) this requires careful planning as there are three amplifiers in the package, and low impedance signal return paths must be provided for each load. (using a parallel combination of 1 m f, 0.1 m f, and 0.01 m f bypass ca- pacitors will help to achieve optimal crosstalk.) the input and output signal return paths (to the bypass caps) must also be kept from overlapping. since ground connections are not of perfectly zero impedance, current in one ground return path can produce a voltage drop in another ground re- turn path if they are allowed to overlap. electric field coupling external to (and across) the package can be reduced by arranging for a narrow strip of ground plane to be run between the pins (parallel to the pin rows). doing this on both sides of the board can reduce the high frequency crosstalk by about 5 db or 6 db. driving capacitive loads when used with the appropriate output series resistor, any load capacitance can be driven without peaking or oscillation. in most cases, less than 50 w is all that is needed to achieve an extremely flat frequency response. as illustrated in figure 44, the AD813 can be very attractive for driving large capacitive loads. in this case, the AD813s high output short circuit cur- rent allows for a 150 v/ m s slew rate when driving a 510 pf capacitor. AD813 4 11 r g r f v in r t v o r l c l r s +v s 0.1 m f 1.0 m f 0.1 m f 1.0 m f Cv s figure 41. circuit for driving a capacitive load
AD813 rev. b C15C overload recovery there are three important overload conditions to consider. they are due to: input common-mode voltage overdrive, out- put voltage overdrive, and input current overdrive. when the amplifier is configured for low closed-loop gains, and the input common-mode voltage range is exceeded, the recovery time will be very fast, typically under 30 ns. when configured for a higher gain, and overloaded at the output, the recovery time will also be short. for example, in a gain of +10, with 6 db of input overdrive, the recovery time of the AD813 is about 25 ns (see figure 45). 0% 2v 1v 50ns 100 90 10 figure 45. 6 db overload recovery, g = +10, (r l = 500 w , r f = 357 w , v s = 5 v) in the case of high gains with very high levels of input overdrive, a longer recovery time will occur. for example, if the input common-mode voltage range is exceeded in the gain of +10, the recovery time will be on the order of 100 ns. this is primarily due to current overloading of the input stage. as noted in the warning under maximum power dissipation, a high level of input overdrive in a high noninverting gain circuit can result in a large current flow in the input stage. though this current is internally limited to about 40 ma, its effect on the total power dissipation may be significant. 1 10 1000 100 frequency C mhz 6 9 3 0 C3 closed-loop gain C db r s = 50 v r s = 30 v r s = 0 v s = 6 5v g = +2 r f = 750 v r l = 1k v c l = 10pf figure 42. response to a small load capacitor at v s = 5 v 1 10 1000 100 frequency C mhz 6 9 3 0 C3 closed-loop gain C db c l = 150pf, r s = 30 v v s = 6 15v g = +2 r f = 750 v r l = 1k v c l = 510pf, r s = 15 v figure 43. response to a large load capacitor at v s = 15 v 5v 5v 100ns 100 100 90 10 0% figure 44. circuit of figure 38 driving a 510 pf load capacitor, v s = 15 v (r l = 1 k w , r f = r g = 750 w , r s =15 w )
AD813 rev. b C16C high performance video line driver at a gain of +2, the AD813 makes an excellent driver for a back terminated 75 w video line. low differential gain and phase errors and wide 0.1 db bandwidth can be realized over a wide range of power supply voltage. excellent gain and group delay matching are also attainable over the full operating supply volt- age range. 75 v 75 v AD813 4 11 r g r f v in v out 75 v +v s 0.1 m f 0.1 m f Cv s 75 v cable 75 v cable figure 46. a video line driver operating at a gain of +2 (r f = r g from table i) g = +2 r l = 150 v 5v 3v 1 10 1000 100 frequency C mhz C1 C6 +1 0 C2 C3 C4 C5 closed-loop gain (normalized) C db +90 0 C90 C180 C270 phase shift C degrees phase gain v s = 6 15v 6 5v v s = 6 15v 6 5v 3v 5v figure 47. closed-loop gain & phase vs. frequency for the line driver 216 14 12 10 8 6 4 supply voltage C volts C3db bandwidth C mhz 40 30 70 50 60 80 90 20 100 110 120 20 18 0 no peaking r f = 590 v r f = 681 v r f = 750 v figure 48. C3 db bandwidth vs. supply voltage for gain = +2, r l = 150 w 100k 1m 100m 10m frequency C hz 0 0.2 0.1 C0.1 C0.2 C0.3 C0.4 normalized gain C db C0.5 3v 6 15v 5v g = +2 r l = 150 v 6 5v figure 49. fine-scale gain (normalized) vs. frequency 1 10 1000 100 frequency C mhz 0 1.0 0.5 C0.5 C1.0 C1.5 C2.0 gain matching C db 1.5 2.0 C2.5 2.5 v s = 6 15v v s = 3v g = +2 r l = 150 v figure 50. closed-loop gain matching vs. frequency 100k 1m 100m 10m frequency C hz 4 2 1.0 0.5 0 C0.5 group delay C ns 6 8 C1.0 10 v s = 6 15v 3v v s = 3v delay delay matching 6 15v 6 5v 5v figure 51. group delay and group delay matching vs. frequency, g = +2, r l = 150 w figures 50 and 51 show the worst case matching; the match between amplifiers 2 and 3 is typically much better than this.
AD813 rev. b C17C disable mode operation pulling the voltage on any one of the disable pins about 2.5 v down from the positive supply will put the corresponding ampli- fier into a disabled, powered down, state. in this condition, the amplifiers quiescent supply current drops to about 0.5 ma, its output becomes a high impedance, and there is a high level of isolation from input to output. in the case of the gain of two line driver for example, the impedance at the output node will be about the same as for a 1.4 k w resistor (the feedback plus gain resistors) in parallel with a 12.5 pf capacitor and the input to output isolation will be about 65 db at 1 mhz. leaving the disable pin disconnected (floating) will leave the corresponding amplifier operational, in the enabled state. the input impedance of the disable pins is about 35 k w in parallel with a few pf. when grounded, about 50 m a flows out of a disable pin on 5 v supplies. input voltages greater than about 1.5 v peak-to-peak will defeat the isolation. in addition, large signals (greater than 3 v peak- to-peak) applied to the output node will cause the output im- pedance to drop significantly. when the disable pins are driven by complementary output cmos logic (such as the 74hc04), the disable time is about 80 ns (until the output goes high impedance) and the enable time is about 100 ns (to low impedance output) on 15 v sup- plies. when operated on 15 v supplies, the disable pins should be driven by open drain logic. in this case, pull-up resis- tors from the disable pins to the plus supply will ensure mini- mum switching time. 75 v 75 v 75 v 75 v v out 75 v cable 1 v in 1 84 v +5v 464 v 590 v 7 4 5 6 select1 2 v in 2 84 v 464 v 590 v 14 12 13 select2 v in 3 84 v 3 464 v 590 v 8 10 9 select3 11 C5v figure 55. a fast switching 3:1 video mux (supply bypassing not shown) operation using a single supply the AD813 will operate with total supply voltages from 36 v down to 2.4 v. with proper biasing (see figure 52) it can make an outstanding single supply video amplifier. since the input and output voltage ranges extend to within 1 v of the supply rails, it will handle a 1.3 v peak-to-peak signal on a single 3.3 v supply, or a 3 v peak-to-peak signal on a single 5 v supply. the small signal 0.1 db bandwidths will exceed 10 mhz in either case, and the large signal bandwidths will exceed 6 mhz. the capacitively coupled cable driver in figure 52 will achieve outstanding differential gain and phase errors of 0.05% and 0.05 degrees respectively on a single 5 v supply. resistor r2, in this circuit, is selected to optimize the differential gain and phase by biasing the amplifier in its most linear region. 75 v AD813 4 11 v in r2 12.4k v v out 75 v +5v 75 v cable c2 1 m f r1 9k v c1 2 m f c3 30 m f 619 v 619 v r3 1k v c out 47 m f figure 52. biasing for single supply operation 1 10 1000 100 frequency C mhz C0.5 C3.0 0.5 0 C1.0 C1.5 C2.0 C2.5 closed-loop gain C db 0 C90 C180 C270 phase shift C degrees C3.5 gain phase v s = 5v g = +2 r f = 619 v r l = 150 v figure 53. closed-loop gain and phase vs. frequency, circuit of figure 52 10 100 0% 500mv 1v 500mv 50ns 90 v in v out figure 54. pulse response for the circuit of figure 52 with +v s = 5 v
AD813 rev. b C18C single supply differential line driver due to its outstanding overall performance on low supply volt- ages, the AD813 makes possible exceptional differential trans- mission on very low power. the circuit of figure 59 will convert a single-ended, ground referenced signal to a differential signal whose common-mode reference is set to one half the supply voltage. this allows for a greater than 2 v peak-to-peak signal swing on a single 3 v power supply. a bandwidth over 30 mhz is achieved with 20 ma of output drive on only 30 mw of quies- cent power (excluding load current). +3v 715 v 715 v 1 m f 2 11 1 m f 715 v 715 v 3 715 v 715 v 1 m f v in 715 v 715 v r l2 v out C 1 4 715 v 10k v 9k v 1k v +3v 1 m f r l1 v out + figure 59. single 3 v supply differential line driver with 2 v swing 10 90 100 0% 1v 1v 50ns v in v out + C v out C figure 60. differential driver pulse response (v s = 3 v, r l1 = r l2 = 200 w ) 3:1 video multiplexer wiring the amplifier outputs together will form a 3:1 mux with outstanding gain flatness. figure 55 shows a recommended configuration which results in C0.1 db bandwidth of 20 mhz and off channel isolation of 60 db at 10 mhz on 5 v sup- plies. the time to switch between channels is about 180 ns. switching time is only slightly affected by signal level. 10 90 100 0% 5v 500mv 500ns figure 56. channel switching characteristic for the 3:1 mux 100k 1m 100m 10m frequency C hz C50 C30 C40 C60 C70 C80 C90 feedthrough C db C20 C10 C100 C110 figure 57. 3:1 mux off channel feedthrough vs. frequency 1 10 100 frequency C mhz C0.5 C3.0 0.5 0 C1.0 C1.5 C2.0 C2.5 closed-loop gain C db 0 C45 C90 C135 phase shift C degrees C180 gain phase figure 58. 3:1 mux on channel gain and phase vs. frequency
AD813 rev. b C19C outline dimensions dimensions shown in inches and (mm). 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 14-lead soic (r-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 printed in u.s.a. c1860bC0C5/98

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